The present invention relates to semiconductor integrated circuits, and more specifically to semiconductor integrated circuits including a high-speed flip-flop circuit capable of scanning.
Flip-flop circuits are commonly employed in semiconductor integrated circuit devices for performing data input/output operations in synchronization with a clock signal. For example, a flip-flop circuit can be used to latch data during a high-level interval of the clock signal and to maintain the latched data during a low-level interval thereof. Alternatively, the contrary case is possible. Since delay time from a point of data input to data output can be long, such flip-flop circuits are not adaptable to high-speed semiconductor integrated circuits.
To address this limitation, a flip-flop circuit based on a pulse (hereinafter, referred to as a pulse-based flip-flop circuit) has been proposed. In normal operation, a clock signal is not directly applied to the pulse-based flip-flop circuit, but rather a pulse signal, generated based on the clock signal is applied thereto. In this embodiment, delay time between data latch and data output is reduced, which enables the pulse-based flip-flop circuit to perform operations (i.e., data latch and maintenance operations) at a faster rate than conventional flip-flop circuits. Therefore, a semiconductor integrated circuit device can operate rapidly using the pulse-based flip-flop circuit.
With increased device integration, it is more and more difficult to test semiconductor integrated circuits because such integrated semiconductor integrated circuits include many input terminals. To achieve testability of the semiconductor integrated circuit, a scan pass method is used. In the scan pass approach, flip-flop circuits are configured to operate as a shift register (hereinafter, referred to as a scan flip-flop circuit). In this method, a value stored in the scan flip-flop circuit is controlled and sampled by a host device under test in a given time period, for example, using a shift function.
To test the semiconductor integrated circuit by means of the scan pass technique, a plurality of scan flip-flop circuits are installed in the semiconductor integrated circuit. The scan flip-flop circuits operate as a flip-flop during normal operation and during a scan test operation of the semiconductor integrated circuit device. Input/output terminals of the scan flip-flops are connected in series to arrange as a shift register circuit. In one example, each of the scan flip-flops is embodied as a pulse-based flip-flop. In general, each of the scan flip-flops performs a normal operation based on a pulse signal and performs a scan test operation based on a clock signal.
Such scan flip-flops are disclosed in the Japanese Patent No. 2003-167030, entitled “SEMICONDUCTOR INTEGRATED CIRCUIT”, and in the Japanese Patent No. 10-177060, entitled “SCANNING CIRCUIT”, respectively.
In the case of a scan flip-flop circuit including a scan mode of operation, operation speed of the semiconductor integrated circuit device may be decreased due to an increase in path delay because of the loading of the additional scan circuit. In addition, when the scan flip-flop circuit is embodied to operate in synchronization with a pulse signal and a clock signal according to the operation modes, mode switch timing may become an issue at the time of switching between the scan test operation and the normal operation.